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Abstract
This paper presents implementation of floating point multiplier using residue number system (RNS). A floating point multiplier has inputs in terms of mantissa and exponent. For multiplication of two inputs, mantissas are multiplied and exponents are needed to be added together. Residue is the remainder obtained after division of two integers. Operations in residue number system are performed on remainders, which are smaller integers. RNS system possesses properties of carry free computation and parallelism which leads to improvement in speed. RNS multiplier unit consist of forward converter, modulo multiplier, modulo adder and reverse converter. A moduli set of the form {2n - 1, 2n, 2n+ 1} is used to find residues of input integers. Input to the system is half precision floating point numbers i.e. sign (1bit), mantissa (10bit), exponent (5bit) and output is a single precision number, sign (1bit), mantissa (23bit), exponent (8bit). The design is coded in Verilog HDL using Xilinx 13.1 ISE software.
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